High speed imaging, for example for scientific applications, is difficult to obtain with traditional image sensors. Back-side illumination (BSI) is a preferred type of CMOS image sensors, because BSI sensors do not have wiring or electronics in front of the photosensitive surface, but behind it. The absence of wiring in front of the photosensitive surface increases the amount of light reaching this photosensitive surface. Thus, BSI sensor are preferred for low illumination conditions and high-speed imaging.
However, power lines, select lines, data lines, switches and related electronic elements for driving and reading the sensing elements are usually laid out at the sides and in between the sensing elements, such as e.g. photodiodes. This reduces the amount of sensing elements that can be laid out in a sensor per unit area. In order to maximize the sensing area on an image sensor, vertical integration (3D IC) technology was developed. 3D stacking provides separation between pixel array and peripheral circuits in different stacked layers, so the surface of the pixel array is effectively utilized. However, the density of connections increases, and row and column circuits may overlap. Moreover, this technology requires advanced and high precision wafer thinning, fabrication of deep and through-silicon vias (TSV), and bonding, e.g. fusion bonding, which should be both easy to implement in a manufacture process and suitable for the particular sensor. Back-side thinning and patterning of wafers is required, as well as back-side metallization for connections between layers, etc. Vias of different diameters can be combined for communication at pad level or between individual blocks on different layers. Shorter interconnects are thereby obtained, which reduces parasitic signals and space required. Thus, 3D stacks can be used for sensors with high spatial resolution.
The document “A 3D stacked CMOS image sensor with 16M pixel global-shutter mode and 2M pixel 10000 fps mode using 4 million interconnections”, by Toni Kondo (Symposium on VLSI, 2015) shows that vertical integration provides global shutter function, and at the same time shielding of the electronics, from both light and photo-generated carriers. It shows a pixel circuit in a bottom layer with a clamp capacitor and a clamp transistor shared by four sample hold capacitors, instead of the usual arrangement of three clamp transistors, thus reducing area. Microbumps are used as interconnection between the pixels and substrates, and the order of millions of bumps can be obtained. The electronic treatment of data is the main speed bottleneck for data processing. Some studies show the possibility of integrating CMOS chips with optical links, using low parasitic capacitance through oxide vias. Although the data transmission is fast and with low energy, the addressing, readout and processing speed is still limited by the electronics of the pixel and readout circuits.